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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. sn74lvc1g06 sces295z ? june 2000 ? revised november 2017 sn74lvc1g06 single inverter buffer/driver with open-drain output 1 1 features 1 ? esd protection exceeds jesd 22 ? 2000-v human body model (a114-a) ? 200-v machine model (a115-a) ? 1000-v charged-device model (c101) ? available in the texas instruments nanofree ? package ? supports 5-v v cc operation ? input and open-drain output accept voltages up to 5.5 v ? maximum t pd of 4.5 ns at 3.3 v at 125 c ? low power consumption, 10- a maximum i cc ? 24-ma output drive at 3.3 v for open-drain devices ? i off supports partial-power-down mode and back- drive protection ? latch-up performance exceeds 100 ma per jesd 78, class ii ? can be used for up or down translation ? schmitt trigger action on all ports 2 applications ? av receivers ? blu-ray players and home theaters ? dvd recorders and players ? desktop or notebook pcs ? digital radio or internet radio players ? digital video cameras (dvc) ? embedded pcs ? gps: personal navigation devices ? mobile internet devices ? network projector front-ends ? portable media players ? pro audio mixers ? smoke detectors ? solid state drive (ssd): enterprise ? high-definition (hdtv) ? tablets: enterprise ? audio docks: portable ? dlp front projection systems ? dvr and dvs ? digital picture frame (dpf) ? digital still cameras 3 description this single inverter buffer and driver is designed for 1.65-v to 5.5-v v cc operation. nanofree package technology is a major breakthrough in ic packaging concepts, using the die as the package. the output of the sn74lvc1g06 device is open- drain and can be connected to other open-drain outputs to implement active-low wired-or or active- high wired-and functions. the maximum sink current is 32 ma. this device is fully specified for partial-power-down applications using i off .the i off circuitry disables the outputs when the device is powered down. this inhibits current backflow into the device which prevents damage to the device. device information (1) part number package body size (nom) sn74lvc1g06dbv sot-23 (5) 2.90 mm 1.60 mm sn74lvc1g06dck sc70 (5) 2.00 mm 1.25 mm sn74lvc1g06drl sot-5x3 (5) 1.60 mm 1.20 mm sn74lvc1g06dry son (6) 1.45 mm 1.00 mm sn74lvc1g06dsf son (6) 1.00 mm x 1.00 mm sn74lvc1g06yzp dsbga (5) 1.40 mm 0.90 mm sn74lvc1g06yzv dsbga (4) 0.90 mm 0.90 mm sn74lvc1g06dpw x2son (5) 0.80 mm x 0.80 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. logic diagram (positive logic) productfolder a y 2 4 support &community tools & software technical documents ordernow referencedesign
2 sn74lvc1g06 sces295z ? june 2000 ? revised november 2017 www.ti.com product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings ............................................................ 4 6.3 recommended operating conditions ...................... 5 6.4 thermal information .................................................. 5 6.5 electrical characteristifcs .......................................... 6 6.6 switching characteristics: ? 40 c to +85 c ............... 6 6.7 switching characteristics: ? 40 c to +125 c ............. 6 6.8 operating characteristics .......................................... 6 6.9 typical characteristics .............................................. 7 7 parameter measurement information .................. 8 8 detailed description .............................................. 9 8.1 overview ................................................................... 9 8.2 functional block diagram ......................................... 9 8.3 feature description ................................................... 9 8.4 device functional modes ........................................ 10 9 application and implementation ........................ 11 9.1 application information ............................................ 11 9.2 typical application ................................................. 11 10 power supply recommendations ..................... 13 11 layout ................................................................... 13 11.1 layout guidelines ................................................. 13 11.2 layout example .................................................... 13 12 device and documentation support ................. 14 12.1 receiving notification of documentation updates 14 12.2 community resources .......................................... 14 12.3 trademarks ........................................................... 14 12.4 electrostatic discharge caution ............................ 14 12.5 glossary ................................................................ 14 13 mechanical, packaging, and orderable information ........................................................... 14 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision y (february 2017) to revision z page ? changed values in the thermal information table to align with jedec standards ............................................................... 5 ? updated feature description to include more detailed information about specific device features. ..................................... 9 ? added dpw layout example ................................................................................................................................................ 13 changes from revision x (august 2015) to revision y page ? changed logic diagram (positive logic) labels from: a-1, y-3 to: a-2, y-4 .......................................................................... 1 ? added receiving notification of documentation updates section ....................................................................................... 14 changes from revision w (december 2013) to revision x page ? added device information table, pin configuration and functions section, esd ratings table, thermal information table, typical characteristics section, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ............................................................... 1 changes from revision v (november 2012) to revision w page ? updated document to new ti data sheet format. ................................................................................................................... 1 ? removed ordering information table. .................................................................................................................................... 1 ? updated i off in features . ......................................................................................................................................................... 1 ? updated operating temperature range. .................................................................................................................................. 5
3 sn74lvc1g06 www.ti.com sces295z ? june 2000 ? revised november 2017 product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated 5 pin configuration and functions dbv package 5-pin sot-23 top view drl package 5-pin sot-5x3 top view dck package 5-pin sc70 top view dpw package 5-pin x2son top view dry package 6-pin son top view dsf package 6-pin son top view yzp package 5-pin dsbga top view yzv package 4-pin dsbga top view (1) nc ? no internal connection (2) see mechanical drawings for dimensions. pin functions (1) (2) pin i/o description name dbv, dck, drl, dpw dry, dsf yzp yzv a 2 2 b1 a1 i input dnu ? ? a1 ? ? do not use gnd 3 3 c1 b1 ? ground nc 1 1 ? ? ? not connected 5 v cc 5 6 a2 a2 ? power pin y 4 4 c2 b2 o output 2 a 1 nc 3 4 gnd y 5 v cc y v cc a nc gnd 2 5 3 4 y 1 a gnd nc v cc nc gnd a v cc y nc 6 5 4 2 3 1 3 4 2 y 1 gnd a nc 5 v cc a gnd nc v cc y c2 c1 b1 a1 a2 a nc nc 6 5 4 2 3 gnd y v cc 1 a gnd y v cc a1 a2 b1 b2
4 sn74lvc1g06 sces295z ? june 2000 ? revised november 2017 www.ti.com product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) the value of v cc is provided in the recommended operating conditions table. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage ? 0.5 6.5 v v i input voltage (2) ? 0.5 6.5 v v o voltage applied to any output in the high-impedance or power-off state (2) ? 0.5 6.5 v v o voltage applied to any output in the high or low state (2) (3) ? 0.5 6.5 v i ik input clamp current v i < 0 ? 50 ma i ok output clamp current v o < 0 ? 50 ma i o continuous output current 50 ma continuous current through v cc or gnd 100 ma t j junction temperature ? 65 150 c t stg storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 1000 machine model (mm), per a115-a 200
5 sn74lvc1g06 www.ti.com sces295z ? june 2000 ? revised november 2017 product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. see implications of slow or floating cmos inputs application report . 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage operating 1.65 5.5 v data retention only 1.5 v ih high-level input voltage v cc = 1.65 v to 1.95 v 0.65 v cc v v cc = 2.3 v to 2.7 v 1.7 v cc = 3 v to 3.6 v 2 v cc = 4.5 v to 5.5 v 0.7 v cc v il low-level input voltage v cc = 1.65 v to 1.95 v 0.35 v cc v v cc = 2.3 v to 2.7 v 0.7 v cc = 3 v to 3.6 v 0.8 v cc = 4.5 v to 5.5 v 0.3 v cc v i input voltage 0 5.5 v v o output voltage 0 5.5 v i ol low-level output current v cc = 1.65 v 4 ma v cc = 2.3 v 8 v cc = 3 v 16 24 v cc = 4.5 v 32 t/ v input transition rise or fall rate v cc = 1.8 v 0.15 v, 2.5 v 0.2 v 20 ns/v v cc = 3.3 v 0.3 v 10 v cc = 5 v 0.5 v 5 t a operating free-air temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) sn74lvc1g06 unit dbv (sot-23) dck (sc70) drl (sot-5x3) dry (son) dpw (x2son) yzv (dsbga) yzp (dsbga) 5 pins 5 pins 5 pins 5 pins 5 pins 4 pins 5 pins r ja junction-to-ambient thermal resistance 231.5 276.1 296.2 369.6 511 168.2 144.4 c/w r jc(top) junction-to-case (top) thermal resistance 139.4 178.9 137.3 257.6 241.9 2.1 1.3 c/w r jb junction-to-board thermal resistance 71.1 70.9 145.3 230.8 374.2 55.9 39.9 c/w jt junction-to-top characterization parameter 45.2 47 14.7 77.2 45 1.1 0.5 c/w jb junction-to-board characterization parameter 70.7 69.3 145.9 231 373.3 56.3 39.7 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a n/a n/a n/a 168 n/a n/a c/w
6 sn74lvc1g06 sces295z ? june 2000 ? revised november 2017 www.ti.com product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated (1) all typical values are at v cc = 3.3 v, t a = 25 c. 6.5 electrical characteristifcs over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ (1) max unit v ol high-level output voltage i ol = 100 a 1.65 v to 5.5 v 0.1 v i ol = 4 ma 1.65 v 0.45 i ol = 8 ma 2.3 v 0.3 i ol = 16 ma 3 v 0.4 i ol = 24 ma 0.55 i ol = 32 ma 4.5 v 0.55 i i inflection- point current v i = 5.5 v or gnd a input 0 to 5.5 v 1 a i off off-state current v i or v o = 5.5 v 0 10 a i cc v i = 5.5 v or gnd, i o = 0 1.65 v to 5.5 v 10 a i cc one input at v cc ? 0.6 v, other inputs at v cc or gnd 3 v to 5.5 v 500 a c i input capacitance v i = v cc or gnd 3.3 v 4 pf c o off-state capacitance v o = v cc or gnd 3.3 v 5 pf 6.6 switching characteristics: ? 40 c to +85 c over recommended operating free-air temperature range, t a = ? 40 c to +85 c (unless otherwise noted) (see figure 3 ) parameter from (input) to (output) v cc min max unit t pd propagation delay a y 1.8 v 0.15 v 2.2 6.5 ns 2.5 v 0.2 v 1.1 4 3.3 v 0.3 v 1.2 4 5 v 0.5 v 1 3 6.7 switching characteristics: ? 40 c to +125 c over recommended operating free-air temperature range, t a = ? 40 c to +125 c (unless otherwise noted) (see figure 3 ) parameter from (input) to (output) v cc min max unit t pd propagation delay a y 1.8 v 0.15 v 2.2 7 ns 2.5 v 0.2 v 1.1 4.5 3.3 v 0.3 v 1.2 4.5 5 v 0.5 v 1 3.5 6.8 operating characteristics t a = 25 c parameter test conditions v cc typ unit c pd power dissipation capacitance f = 10 mhz 1.8 v 3 pf 2.5 v 3 3.3 v 4 5 v 6
7 sn74lvc1g06 www.ti.com sces295z ? june 2000 ? revised november 2017 product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated 6.9 typical characteristics figure 1. tpd across temperature at 3.3-v v cc figure 2. tpd across v cc at 25 c temperature - c tpd - ns -100 -50 0 50 100 150 0 0.5 1 1.5 2 2.5 d001 tpd vcc - v tpd - ns 0 1 2 3 4 5 6 0 1 2 3 4 5 6 d002 tpd
8 sn74lvc1g06 sces295z ? june 2000 ? revised november 2017 www.ti.com product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated 7 parameter measurement information figure 3. load circuit and voltage waveforms (open drain) v m t h t su from output under t est c l (see note a) load circuit s1 v load open gnd r l r l data input t iming input v i 0 v v i 0 v 0 v t w input volt age w aveforms setup and hold times volt age w aveforms propaga tion dela y times inverting and noninverting outputs volt age w aveforms pulse dura tion t plh t phl t phl t plh v oh v oh v ol v ol v i 0 v input output w aveform 1 s1 at v load (see note b) output w aveform 2 s1 at v load (see note b) v ol t pzl t pzh t plz t phz v load /2 0 v v ol + v v load/2 ? v 0 v v i volt age w aveforms enable and disable times low - and high-level enabling outputoutput notes: a. c l includes probe and jig capacitance. b. w aveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 . d. the outputs are measured one at a time, with one transition per measurement. e. since this device has open-drain outputs, t plz and t pzl are the same as t pd . f. t pzl is measured at v m . g. t plz is measured at v ol + v . h. all parameters and waveforms are not applicable to all devices. output control v m v m v m v m v m v m v m v m v m v m v m v m v i v m v m 1.8 v 0.15 v 2.5 v 0.2 v 3.3 v 0.3 v 5 v 0.5 v 1 k 500 500 500 v cc r l 2 v cc 2 v cc 6 v 2 v cc v load c l 30 pf30 pf 50 pf 50 pf 0.15 v0.15 v 0.3 v0.3 v v v cc v cc 3 v v cc v i v cc /2 v cc /2 1.5 v v cc /2 v m t r /t f 2 ns 2 ns 2.5 ns 2.5 ns input t pzl (see notes e and f) t plz (see notes e and g) t phz /t pzh v load v load v load test s1 v load /2
9 sn74lvc1g06 www.ti.com sces295z ? june 2000 ? revised november 2017 product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated 8 detailed description 8.1 overview the sn74lvc1g06 device contains one open-drain inverter with a maximum sink current of 32 ma. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs when the device is powered down. this inhibits current backflow into the device which prevents damage to the device. 8.2 functional block diagram figure 4. logic diagram (positive logic) 8.3 feature description 8.3.1 cmos open-drain outputs the open-drain output allows the device to sink current to gnd but not to source current from v cc . when the output is not actively pulling the line low, it will go into a high impedance state (tri-state). this allows the device to be used for a wide variety of applications, including up-translation and down-translation, as the output voltage can be determined by an external pullup. the drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. it is important for the power output of the device to be limited to avoid thermal runaway and damage due to over-current. the electrical and thermal limits defined in the absolute maximum ratings must be followed at all times. 8.3.2 standard cmos inputs the impendence for standard cmos inputs is high. typically, a cmos input is modeled as a resistor in parallel with the input capacitance as shown in the electrical characteristics . the worst case resistance is calculated with the maximum input voltage, given in the absolute maximum ratings , and the maximum input leakage current, given in the electrical characteristics , using ohm's law (r = v i). signals applied to the inputs need to have fast edge rates, as defined by t/ v in the recommended operating conditions to avoid excessive current consumption and oscillations. if a slow or noisy input signal is required, a device with a schmitt-trigger input should be used to condition the input signal before the standard cmos input. a y 2 4
10 sn74lvc1g06 sces295z ? june 2000 ? revised november 2017 www.ti.com product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated feature description (continued) 8.3.3 negative clamping diodes the inputs and outputs to this device have negative clamping diodes as depicted in figure 5 . caution voltages beyond the values specified in the absolute maximum ratings table can cause damage to the device. the input negative-voltage and the output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. figure 5. electrical placement of clamping diodes for each input and output 8.3.4 partial power down (i off ) each input and output enter a high impedance state when the supply voltage is 0 v. the maximum leakage into or out of any input or output pin on the device is specified by i off in the electrical characteristics . 8.3.5 over-voltage tolerant inputs input signals to this device can be driven above the supply voltage as long as the input signals remain below the maximum input voltage value specified in the recommended operating conditions . 8.4 device functional modes table 1 lists the functional modes of the sn74lvc1g06. table 1. function table input a output y l hi-z h l gnd logic input output v cc device -i ik -i ok
11 sn74lvc1g06 www.ti.com sces295z ? june 2000 ? revised november 2017 product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the sn74lvc1g06 is a high-drive cmos device that can be used to implement a high output drive buffer, such as an led application. it can sink 32 ma of current at 4.5 v making it ideal for high-drive applications. it is good for high-speed applications up to 100 mhz. the inputs are 5.5-v tolerant allowing it to translate up or down to v cc . below shows a simple led driver application for a single channel of the device. 9.2 typical application figure 6. typical application diagram 9.2.1 design requirements this device uses cmos technology and has balanced output drive. take care to avoid bus contention because it can drive currents that would exceed maximum limits. the high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing. 9.2.2 detailed design procedure 1. recommended input conditions ? rise time and fall time specs. see ( t/ v) in the recommended operating conditions table. ? specified high and low levels. see (v ih and v il ) in the recommended operating conditions table. ? inputs are overvoltage tolerant allowing them to go as high as (v i max) in the recommended operating conditions table at any valid v cc . 2. recommended output conditions ? load currents should not exceed (i o max) per output and should not exceed (continuous current through v cc or gnd) total current for the part. these limits are located in the absolute maximum ratings table. ? outputs should not be pulled above 5.5 v. vpu from mcu v cc
12 sn74lvc1g06 sces295z ? june 2000 ? revised november 2017 www.ti.com product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated typical application (continued) 9.2.3 application curve figure 7. i cc vs frequency frequency - mhz icc - a 0 20 40 60 80 0 200 400 600 800 1000 1200 1400 1600 d001 icc 1.8v icc 2.5v icc 3.3v icc 5v
13 sn74lvc1g06 www.ti.com sces295z ? june 2000 ? revised november 2017 product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated 10 power supply recommendations the power supply can be any voltage between the minimum and maximum supply voltage rating located in the recommended operating conditions table. the v cc pin must have a good bypass capacitor to prevent power disturbance. a 0.1- f capacitor is recommended, and it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1- f and 1- f capacitors are commonly used in parallel. the bypass capacitor must be installed as close to the power pin as possible for best results. 11 layout 11.1 layout guidelines even low data rate digital signals can contain high-frequency signal components due to fast edge rates. when a printed-circuit board (pcb) trace turns a corner at a 90 angle, a reflection can occur. a reflection occurs primarily because of the change of width of the trace. at the apex of the turn, the trace width increases to 1.414 times the width. this increase upsets the transmission-line characteristics, especially the distributed capacitance and self ? inductance of the trace which results in the reflection. not all pcb traces can be straight and therefore some traces must turn corners. figure 8 shows progressively better techniques of rounding corners. only the last example (best) maintains constant trace width and minimizes reflections. an example layout is given in figure 9 for the dpw (x2son-5) package. this example layout includes a 0402 (metric) capacitor and uses the measurements found in the example board layout appended to this end of this datasheet. a via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. this via can be used to trace out the center pin connection through another board layer, or it can be left out of the layout 11.2 layout example figure 8. trace example figure 9. example layout with dpw (x2son-5) package worst better best solder mask opening, typ metal under solder mask, typ 8 mil 4 mil 8 mil 0402 0.1 ? f bypass capacitor 8 mil
14 sn74lvc1g06 sces295z ? june 2000 ? revised november 2017 www.ti.com product folder links: sn74lvc1g06 submit documentation feedback copyright ? 2000 ? 2017, texas instruments incorporated 12 device and documentation support 12.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks nanofree, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser based versions of this data sheet, refer to the left hand navigation.
package option addendum www.ti.com 30-dec-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples psn74lvc1g06dpwr active x2son dpw 5 3000 tbd call ti call ti -40 to 85 sn74lvc1g06dbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (c065, c06f, c06r, c06t) (c06h, c06p, c06s) sn74lvc1g06dbvre4 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c06f sn74lvc1g06dbvrg4 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c06f sn74lvc1g06dbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (c065, c06f, c06r) (c06h, c06p, c06s) sn74lvc1g06dbvtg4 active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c06f sn74lvc1g06dckr active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ct5, ctf, ctk, ct r, ctt) (cth, cts) sn74lvc1g06dckre4 active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ct5, ctf, ctk, ct r, ctt) (cth, cts) sn74lvc1g06dckrg4 active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ct5, ctf, ctk, ct r, ctt) (cth, cts) sn74lvc1g06dckt active sc70 dck 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ct5, ctf, ctk, ct r) (cth, cts) sn74lvc1g06dckte4 active sc70 dck 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ct5, ctf, ctk, ct r) (cth, cts) sn74lvc1g06dcktg4 active sc70 dck 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ct5, ctf, ctk, ct r) (cth, cts) sn74lvc1g06dpwr active x2son dpw 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 co
package option addendum www.ti.com 30-dec-2017 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples sn74lvc1g06drlr active sot-5x3 drl 5 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 (ct7, ctr) sn74lvc1g06dryr active son dry 6 5000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ct sn74lvc1g06dsfr active son dsf 6 5000 green (rohs & no sb/br) cu nipdau | cu nipdauag level-1-260c-unlim -40 to 125 ct sn74lvc1g06yzpr active dsbga yzp 5 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 ctn sn74lvc1g06yzvr active dsbga yzv 4 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 ct n (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 30-dec-2017 addendum-page 3 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of sn74lvc1g06 : ? enhanced product: SN74LVC1G06-EP note: qualified version definitions: ? enhanced product - supports defense, aerospace and medical applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn74lvc1g06dbvr sot-23 dbv 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 q3 sn74lvc1g06dbvr sot-23 dbv 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 sn74lvc1g06dbvr sot-23 dbv 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 sn74lvc1g06dbvrg4 sot-23 dbv 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 sn74lvc1g06dbvt sot-23 dbv 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 q3 sn74lvc1g06dbvt sot-23 dbv 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 sn74lvc1g06dbvt sot-23 dbv 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 sn74lvc1g06dbvtg4 sot-23 dbv 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 sn74lvc1g06dckr sc70 dck 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74lvc1g06dckr sc70 dck 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 q3 sn74lvc1g06dckt sc70 dck 5 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 q3 sn74lvc1g06dckt sc70 dck 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74lvc1g06dpwr x2son dpw 5 3000 178.0 8.4 0.91 0.91 0.5 2.0 8.0 q3 sn74lvc1g06drlr sot-5x3 drl 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 q3 sn74lvc1g06drlr sot-5x3 drl 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 q3 sn74lvc1g06dryr son dry 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 q1 sn74lvc1g06dsfr son dsf 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 sn74lvc1g06yzpr dsbga yzp 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 q1 package materials information www.ti.com 23-dec-2017 pack materials-page 1
device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn74lvc1g06yzvr dsbga yzv 4 3000 178.0 9.2 1.0 1.0 0.63 4.0 8.0 q1 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn74lvc1g06dbvr sot-23 dbv 5 3000 180.0 180.0 18.0 sn74lvc1g06dbvr sot-23 dbv 5 3000 180.0 180.0 18.0 sn74lvc1g06dbvr sot-23 dbv 5 3000 202.0 201.0 28.0 sn74lvc1g06dbvrg4 sot-23 dbv 5 3000 180.0 180.0 18.0 sn74lvc1g06dbvt sot-23 dbv 5 250 180.0 180.0 18.0 sn74lvc1g06dbvt sot-23 dbv 5 250 180.0 180.0 18.0 sn74lvc1g06dbvt sot-23 dbv 5 250 202.0 201.0 28.0 sn74lvc1g06dbvtg4 sot-23 dbv 5 250 180.0 180.0 18.0 sn74lvc1g06dckr sc70 dck 5 3000 180.0 180.0 18.0 sn74lvc1g06dckr sc70 dck 5 3000 180.0 180.0 18.0 sn74lvc1g06dckt sc70 dck 5 250 205.0 200.0 33.0 sn74lvc1g06dckt sc70 dck 5 250 180.0 180.0 18.0 sn74lvc1g06dpwr x2son dpw 5 3000 205.0 200.0 33.0 sn74lvc1g06drlr sot-5x3 drl 5 4000 202.0 201.0 28.0 sn74lvc1g06drlr sot-5x3 drl 5 4000 184.0 184.0 19.0 sn74lvc1g06dryr son dry 6 5000 184.0 184.0 19.0 package materials information www.ti.com 23-dec-2017 pack materials-page 2
device package type package drawing pins spq length (mm) width (mm) height (mm) sn74lvc1g06dsfr son dsf 6 5000 184.0 184.0 19.0 sn74lvc1g06yzpr dsbga yzp 5 3000 220.0 220.0 35.0 sn74lvc1g06yzvr dsbga yzv 4 3000 220.0 220.0 35.0 package materials information www.ti.com 23-dec-2017 pack materials-page 3

www.ti.com package outline c 4x 0.27 0.17 3x 0.32 0.23 0.4 max 0.05 0.00 2x 0.48 0.27 0.17 0.25 0.1 b 0.85 0.75 a 0.85 0.75 (0.1) (0.06) 4x (0.05) (0.25) 2x (0.26) x2son - 0.4 mm max height dpw0005a plastic small outline - no lead 4223102/b 09/2017 pin 1 index area seating plane note 3 1 2 3 4 0.1 c a b 0.05 c 5 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. the size and shape of this feature may vary. note 3 scale 12.000
www.ti.com example board layout 0.05 min all around typ (0.21) typ exposed metal clearance (0.48) (0.78) 4x (0.42) 4x (0.22) ( 0.25) 4x (0.26) 4x (0.06) ( 0.1) via (r0.05) typ x2son - 0.4 mm max height dpw0005a plastic small outline - no lead 4223102/b 09/2017 symm 1 2 3 4 symm land pattern example solder mask defined scale:60x solder mask opening, typ metal under solder mask typ 5 notes: (continued) 4. this package is designed to be soldered to a thermal pad on the board. for more information, refer to qfn/son pcb application note in literature no. slua271 (www.ti.com/lit/slua271).
www.ti.com example stencil design (0.48) (0.78) 4x (0.42) 4x (0.22) 4x (0.26) 4x (0.06) ( 0.24) (0.21) typ (r0.05) typ x2son - 0.4 mm max height dpw0005a plastic small outline - no lead 4223102/b 09/2017 notes: (continued) 5. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. solder paste example based on 0.1 mm thick stencil exposed pad 92% printed solder coverage by area scale:100x symm 1 2 3 4 symm edge solder mask 5
www.ti.com package outline c 0.5 max 0.19 0.15 1 typ 0.5 typ 5x 0.25 0.21 0.5 typ b e a d 4219492/a 05/2017 dsbga - 0.5 mm max height yzp0005 die size ball grid array notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. ball a1 corner seating plane ball typ 0.05 c b 1 2 0.015 c a b symm symm c a scale 8.000d: max = e: max = 1.418 mm, min = 0.918 mm, min = 1.358 mm0.858 mm
www.ti.com example board layout 5x ( 0.23) (0.5) typ (0.5) typ ( 0.23) metal 0.05 max ( 0.23) solder mask opening 0.05 min 4219492/a 05/2017 dsbga - 0.5 mm max height yzp0005 die size ball grid array notes: (continued) 3. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number snva009 (www.ti.com/lit/snva009). symm symm land pattern example scale:40x 1 2 a b c non-solder mask defined (preferred) solder mask details not to scale solder mask opening solder mask defined metal under solder mask
www.ti.com example stencil design (0.5) typ (0.5) typ 5x ( 0.25) (r0.05) typ metal typ 4219492/a 05/2017 dsbga - 0.5 mm max height yzp0005 die size ball grid array notes: (continued) 4. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. symm symm solder paste example based on 0.1 mm thick stencil scale:40x 1 2 a b c
d: max = e: max = 0.918 mm, min = 0.918 mm, min = 0.858 mm0.858 mm

www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal
www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2

www.ti.com c 6x 0.22 0.12 6x 0.45 0.35 2x 0.7 4x 0.35 0.4 max 0.05 0.00 a 1.05 0.95 b 1.05 0.95 (0.11) typ (0.1) pin 1 id 4208186/f 10/2014 pin 1 index area seating plane 0.05 c 1 3 4 6 0.07 c a b 0.05 c symm symm notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. reference jedec registration mo-287, variation x2aaf. mechanical data dsf (s-px2son-n6) plastic small outline no-lead

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